Abstract
<jats:p>Modern electronic assembly manufacturing relies on complex global supply chains, making it increasingly important to verify that every assembled component is authentic, expected, and consistent with the intended design. Existing automated inspection approaches typically formulate this problem as a classification task, providing limited insight into the physical evidence supporting their conclusions and often failing to distinguish expected manufacturing variation from genuine hardware integrity events. This paper presents a scenario-based method for hardware integrity verification that formulates component verification as an evidence-based reasoning process. Independent semantic observations and learned visual evidence are extracted from standard manufacturing images and evaluated against the expected observations associated with candidate manufacturing and hardware integrity scenarios, including normal production evolution, approved AVL substitutions, unexpected component changes, and counterfeit-related events. The method was developed using more than 6.5 billion component images collected from high-volume SMT manufacturing and enables transparent, explainable hardware integrity assessments. Representative examples demonstrate that the proposed methodology distinguishes expected manufacturing changes from hardware integrity violations using only standard production images. By automatically inspecting, identifying, verifying, and documenting every component assembled on every PCB, the proposed methodology establishes a practical foundation for component-level hardware assurance. The resulting digital record provides traceable forensic evidence for every assembled component, enabling scalable hardware integrity verification throughout the electronic assembly manufacturing process.</jats:p>